Performance Evaluation and Limitations of a Vision System on a Reconfigurable/Programmable Chip

This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (fpga). system limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. the system hereby reported has a conventional architecture. it consists in a central microprocessor (cpu) and the necessary peripheral elements for data acquisition, data storage and communications. it has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (pc) is provided. in order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. it operates autonomously, commanded by the cpu, as another system peripheral. the complete system, without the sensor, has been implemented in a single reconfigurable chip as a sopc. the incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. however, time-multiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. we have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware.