a power-efficient noise-tolerant circuit technique for wide dynamic gates

In this article, a dynamic circuit technique is suggested to lower the consumed power of wide gates without speed degradation. in the proposed circuit, the voltage swing on the evaluation network is reduced to decrease the consumed power of wide gates. to reduce the consumed power and delay of the suggested circuit, the structure of the output inverter is modified by utilizing the voltage of the footer node of the evaluation network. a current mirror is employed to decrease the contention between the evaluation network and keeper transistors, replicating the evaluation network's leakage current. in addition, the subthreshold leakage current is reduced due to the stacking effect. as a result, the leakage power is lowered and the noise immunity is improved. wide or gates are simulated using hspice in a 90nm cmos technology. simulation results of wide or gates demonstrate 51% power reduction and 1.82× noise immunity improvement at the same delay as the conventional dynamic circuit for 32-input or gates. moreover, a 128-input multiplexer is designed by employing the suggested dynamic circuit. the results demonstrate 13% power reduction and 33% speed improvement for the suggested 128-input multiplexer compared to the conventional multiplexer at the same robustness.