dmr-based technique for fault tolerant aes s-box architecture

This paper presents a high-throughput fault-resilient hardware implementation of aes s-box, called hfs-box. we propose deep pipelining s-box in the gate level in which a novel dmr technique is used for fault correction. proposed fault-resilient technique is based on fault correction in dmr implementation (fc-dmr) of each s-box’s combined with a temporal redundancy technique. if a transient natural or even malicious fault(s) in each pipeline stage is detected, the corresponding error signal become high and as a result the control unit holds the output of our proposed dmr voter till the fault effect disappears. proposed low-cost hfs-box provide a high capability of fault tolerant against transient faults with any duration by putting low area overhead, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original implementation.