improving efficiency and reducing clock speed requirement simultaneously in delta sigma modulator transmitter

This paper introduces an architecture to enhance efficiency and reduce clock speed requirement of the delta–sigma modulator (dsm)–transmitters. for this purpose, the quantization noise reduction technique and timeinterleaved parallel dsm are used. by using this combined technique with four-branch time-interleaved dsm for an long-term evolution (lte) signal with 1.92 mhz bandwidth, 7.8 db peak to average power ratio (papr) and an oversampling ratio (osr) of 16, the coding efficiency (ce) of transmitter is improved from 9.7% to 22.3% with 42db signal to noise and distortion ratio (sndr) while the clock speed is only 7.68 mhz. it is four times lower than the clock speed requirement of conventional dsm to achieve the same sndr.