high-speed and low-voltage 16-t dynamic full adder cell based on finfet transistors

In this paper, an optimized design of dynamic logic using finfet transistors for one-bit full adder cell is presented. the proposed full adder was simulated in 32 nm technology by considering various conditions in terms of supply voltage, capacitive loads and temperature changes. based on the obtained results, it was determined that the proposed full adder is faster compared to other full adders and has a low power delay product (pdp) than the compared structures. the proposed full adder can still work well at 0.3v supply voltage. based on the simulation results, at the supply voltage of 0.3 v and the load capacitors from 1.4 to 9.4 ff, the propagation delay is in the range of 151.75 to 248.25 ps, the average power consumption is in the range of 89.95 to 238.80 nw, and the pdp varies from 13.65 to 59.28 aj. the amount of leakage power in this operating voltage is equal to 5.63 nw. the values obtained at the supply voltage of 0.3 v indicate the excellent performance of the proposed 16-transistor dynamic full adder, which makes it a candidate for high-speed low-voltage applications