A high level implementation and performance evaluation of level-I asynchronous cache on FPGA

To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. cache is responsible for a major part of energy consumption (approx. 50%) of processors. this paper presents a high level implementation of a micropipelined asynchronous architecture of l1 cache. due to the fact that each cache memory implementation is time consuming and errorprone process, a synthesizable and a configurable model proves out to be of immense help as it aids in generating a range of caches in a reproducible and quick fashion. the micropipelined cache, implemented using c-elements acts as a distributed message-passing system. the rtl cache model implemented in this paper, comprising of data and instruction caches has a wide array of configurable parameters. in addition to timing robustness our implementation has high average cache throughput and low latency. the implemented architecture comprises of two direct-mapped, write-through caches for data and instruction. the architecture is implemented in a field programmable gate array (fpga) chip using very high speed integrated circuit hardware description language (vhsic hdl) along with advanced synthesis and place-and-route tools.