design of current starved voltage controlled oscillator with phase locked loop to estimate the process corner analysis

This paper consists of a performance comparison of current starved voltage controlled oscillator (csvco) for phase locked loop (pll). the design of current starved vco is implemented using sleepy stack low power leakage technique. this has been implemented in 45nm cmos technology with a supply voltage of 0.45v in cadence software. the parameters such as average power, oscillation frequency, and delay are calculated in different process corners showing the performance of improvement results of cadence simulation. after comparison of the various parameters of pll implemented with sleep stack csvco and basic csvco, the sleepy stack approach is particularly useful in low power applications, the recommended pll has a much smaller chip than previous designs, much lower power consumption and significantly higher efficiency. the proposed design of the pll with sleep stack technique makes the circuit efficiently to reduce sub-threshold leakage current, and achieves frequency of 2.759 ghz, power 2.559µw, phase noise -63.8(dbc/hz) and delay(µs) 0.0006544, respectively.