𝚫Σ Fractional-N Synthesizer for GSM-E-900 Frequency Standard

This paper presents an integrated phase-locked loop (pll) frequency synthesizer for wireless communication application in standard 0.18 μm cmos process. delta sigma modulator used for reducing phase noise. the use of δσ modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-n division. the this technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional−n pll techniques. simulation results show that the phase noise of frequency synthesizer is -108 𝑑𝐵𝐶𝐻𝑧@1mhz offset, and the pll synthesizer provides output frequencies 880-915 mhz in uplink and 925-960 mhz in downlink. fref is 26 mhz and channel spicing is 700 khz. moreover, benefiting from the combination of current-mode-logic (cml) the pll consumes a total power dissipation of only 24.35 mw with a single 1.8 v supply including all the buffers. although prescaler increases settling time (ts), it decreases power consumptions. settling time in uplink is 425 ns and in downlink about 475 ns.