design and simulation of a fully integrated, low-power, 2.5gb/s optical front-end

This paper, describes a cmos trans-impedance amplifier (tia) and limiting amplifier (la) for 2.5gb/s, low-power opto-electronic communication receiver systems. the single ended tia, which benefits form active type of inductors, is designed and simulated using 0.18μm cmos process parameters. the proposed circuits are analyzed mathematically and all necessary simulations for proving the proper performance of the proposed tia stage and the proposed la stage such as eye-diagram, montecarlo and noise analysis are done. simulation results in hspice show the trans-impedance gain of 45.5dbω, frequency bandwidth of 1.85ghz and power consumption of 1.1mw at 1.5v supply for the tia stage and 87db gain and 2ghz frequency bandwidth for the whole receiver system, which consumes only 7.3mw power. results indicate that the proposed circuits are suitable to work as a low-power building block as opto-electrical communication receiver.