Fast Lock and Settling Time Improvement for Indirect Frequency Synthesizer Phase Locked Loop

Settling time is one of the major quality feature in phase locked loop frequency synthesizer (pll-fs). additionally, fast lock is very important for pll in multiple applications. when pll in lock range becomes as fast as possible, it gives no error in a comparison process; and the system works probably. in this paper, a new design of indirect phase locked loop frequency synthesizer circuit is proposed to minimize the settling time at pll-fs output signal when there is a sudden change in frequency. in this work, a great improvement is achieved to speed up the lock-in time of the circuit. the proposed design improves the settling time up to 80% at output frequency; and the lock- time speed is increased. orcad and matlab simulators are used to show the proposed design validity.