optimization of a new extended cascaded multilevel inverter topology to reduce dc voltage sources and power electronic components

This work proposes a new multilevel inverter consisting of basic and sub-multilevel units. the basic unit is madeup of four isolated dc voltage sources, two bidirectional switches and ten unidirectional switches. to increase the number of the output voltage levels, a cascaded architecture based on series connection of sub-multilevel is proposed. the proposed inverter utilizes two algorithms to determine the values of dc voltage sources. number of igbts, dc voltage sources, gate driver circuits, variety of dc voltage sources and peak standing voltage on the switches are calculated and their optimization to produce maximum number of levels in output voltage is investigated. to examine advantages of the proposed inverter, the topology is compared with other topologies. the results show superiority of proposed topology over most conventional topologies, in number of circuit components. finally, to confirm the performance of the proposed multilevel inverter, experimental results of a 25-level inverter prototype are provided.