a new multilevel inverter topology with component count reduction

As a major component of electrical systems, multilevel inverters have been discussed extensively over the past decade. nowadays, the improvement of their performance is one of the important challenges that has brought about many studies on their topology and control system. this paper proposes a new topology of symmetrical multi-level inverters that is able to feed inductive, resistive and capacitive loads. the proposed topology has fewer power elements including igbts, driver circuits, diodes, and dc voltage sources. to increase the number of output voltage levels, several basic topologies can be used in a cascaded structure. the comparison of the proposed converter with some previous topologies shows its better conditions in terms of the used semiconductor count, switching and conduction losses, and total blocking voltage. the operation and performance of the proposed multi-level inverter are ascertained by simulations and are verifiedexperimentally for a 9-level inverter, showing the capability of the proposed converter in smooth sinusoidal output voltage generation with a minimum total harmonic distortion.