A hardware architecture of a counter-based entropy coder

This paper describes a hardware architectural design of a real-time counter based entropy coder at a register transfer level (rtl) computing model. the architecture is based on a lossless compression algorithm called rice coding,which is optimal for an entropy range of 1.5 < h < 2.5 bits per sample. the architecture incorporates a word-splitting scheme to extend the entropy coverage into a range of 1.5 < h < 7.5 bits per sample. we have designed a data structure in a form of independent code blocks,allowing more robust compressed bitstream. the design focuses on an rtl computing model and architecture,utilizing 8-bit buffers,adders,registers,loader-shifters,select-logics,down-counters,up-counters,and multiplexers. we have validated the architecture (both the encoder and the decoder) in a coprocessor for 8 bits/sample data on an fpga xilinx xc4005,utilizing 61% of f&g-clbs,34% h-clbs,32% ff-clbs,and 68% io resources. on this fpga implementation,the encoder and decoder can achieve 1.74 mbits/s and 2.91 mbits/s throughputs,respectively. the architecture allows pipelining,resulting in potentially maximum encoding throughput of 200 mbit/s on typical real-time ttl implementations. in addition,it uses a minimum number of register elements. as a result,this architecture can result in low cost,low energy consumption and reduced silicon area realizations. © 2012 published by lppm itb & pii.