Comparison of memory assignment schemes for switch architectures with shareable parallel memory modules

Switching architectures deploying shareable parallel memory modules are quite versatile in their ability to scale to higher capacity while retaining the advantage of sharing its entire memory resource among all input and output ports. the two main classes of such architectures,namely,the shared multibuffer-(smb-) based switch and the sliding-window-(sw-) based packet switch,both deploy parallel memory modules that are physically separate but logically connected. inspite of their similarity in regards to using shareable parallel memory modules,they differ in switching control and scheduling of packets to parallel memory modules. smb switch uses centralized control whereas the sw switch uses a decentralized control for switching operations. in this paper,we present a new memory assignment scheme for the sliding-window (sw) switch for assigning packets to parallel memory modules that maximizes the parallel storage of packets to multiple memory modules. we compare the performance of a sliding-window switch deploying this new memory assignment scheme with that of an smb switch architecture under conditions of identical traffic type and memory resources deployed. the simulation results show that the new memory assignment scheme for the sliding window switch maximizes parallel storage of packets input in a given switch cycle,and it does not require speed-up of memory modules. furthermore,it provides a superior performance compared to that of the smb switch under the constraints of fixed memory-bandwidth and memory resources. © 2010 s. kumar and a. munoz.