New low-power tristate circuits in positive feedback source-coupled logic

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (pfscl) have been proposed. the first one is a switch-based technique while the second is based on the concept of sleep transistor. different tristate circuits based on both techniques have been developed and simulated using 0.18m cmos technology parameters. a performance comparison indicates that the tristate pfscl circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to cmos-based and the switch-based pfscl circuits. © 2011 kirti gupta et al.