An interpolated flying-adder-based frequency synthesizer

This work presents an interpolated flying-adder- (fa-) based frequency synthesizer. the architecture of an interpolated fa,which uses an interpolated multiplexer (mux) to replace the multiplexer in conventional flying adder,improves the cycle-to-cycle jitter and root-mean-square (rms) jitter performance. a multiphase all-digital phase-locked loop (adpll) provides steady reference signals for the interpolated flying adder. this paper reveals implementation skills of a multiphase adpll,as well as an interpolated flying adder. in addition,analytical details of the jitter performance are derived. a test chip for the proposed interpolated fa-based frequency synthesizer was fabricated in a standard 0.18m cmos technology,and the core area was 0.143mm 2. the output frequency had a range of 33mhz ∼ 286mhz at 1.8v with peak-to-peak (p k - p k) jitter 215.2ps at 286mhz/1.8v. © 2011 pao-lung chen and chun-chien tsai.