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Semidigital PLL design for low-cost low-power clock generation
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نویسنده
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xu n. ,rhee w. ,wang z.
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منبع
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journal of electrical and computer engineering - 2011 - شماره : 0
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چکیده
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This paper describes recent semidigital architectures of the phase-locked loop (pll) systems for low-cost low-power clock generation. with the absence of the time-to-digital converter (tdc),the semi-digital pll (sdpll) enables low-power linear phase detection and does not necessarily require advanced cmos technology while maintaining a technology scalability feature. two design examples in 0.18m cmos and 65nm cmos are presented with hardware and simulation results,respectively. © 2011 ni xu et al.
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آدرس
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institute of microelectronics,tsinghua university, China, institute of microelectronics,tsinghua university, China, institute of microelectronics,tsinghua university, China
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Authors
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