A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency islands

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect,and hence reducing them is an important problem. application-specific designs have nonuniform network utilization,thereby requiring a buffer-sizing approach that tackles the nonuniformity. also,congestion effects that occur during network operation need to be captured when sizing the buffers. many nocs are designed to operate in multiple voltage/frequency islands,with interisland communication taking place through frequency converters. to this end,we propose a two-phase algorithm to size the switch buffers in network-on-chips (nocs) considering support for multiple-frequency islands. our algorithm considers both the static and dynamic effects when sizing buffers. we analyze the impact of placing frequency converters (fcs) on a link,as well as pack and send units that effectively utilize network bandwidth. experiments on many realistic system-on-chip (soc) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach. copyright © 2012 anish s. kumar et al.