VLSI architectures for sliding-window-based space-time turbo trellis code decoders

The vlsi implementation of siso-map decoders used for traditional iterative turbo coding has been investigated in the literature. in this paper,a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. these architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (acso) unit,a-,b-,ω-,and llr output calculation modules. measurements of complexity and decoding delay of several sliding-window-technique-based map decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures. copyright © 2012 georgios passas and steven freear.