Hybrid model: An efficient symmetric multiprocessor reference model

Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems,particularly for symmetric multiprocessors. it is estimated that verification in its entirety accounts for up to 60% of design resources,including duration,computer resources,and total personnel. simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. the greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. in this paper,we propose an efficient symmetric multiprocessor reference model,hybrid model,written with systemc. systemc can provide a high-level simulation environment and is faster than the traditional hardware description languages. hybrid model has been implemented in an efficient 32-bit symmetric multiprocessor verification. experimental results show our proposed model is a fast,accurate,and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately. © 2015 shupeng wang et al.