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Wu's characteristic set method for SystemVerilog assertions verification
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نویسنده
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gao x. ,zhou n. ,wu j. ,li d.
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منبع
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journal of applied mathematics - 2013 - دوره : 2013 - شماره : 0
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چکیده
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We propose a verification solution based on characteristic set of wu's method towards systemverilog assertion checking over digital circuit systems. we define a suitable subset of svas so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. we present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. this symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation. © 2013 xinyan gao et al.
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آدرس
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school of software,dalian university of technology, China, school of computer and information technology,beijing jiaotong university,beijing 10044,china,school of electronic and information engineering,lanzhou jiaotong university, China, guangxi key laboratory of hybrid computation and ic design analysis,guangxi university for nationalities, China, school of software,dalian university of technology, China
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Authors
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