Design of low power VLSI circuits for precharge logic

Secure communication is very important in the present world. although the power minimization has become a primary concern,it is not the most important design factor in many cases. for example,security is the main goal when designing cryptographic hardware. in one hand,cryptographic hardware is threatened strongly by several side channel attack (sca) scenarios and especially differential power analysis (dpa) attacks. on the other hand,cryptographic vlsi systems are energy consuming. this makes them limited and inefficient for power critical applications,particularly in portable battery operated systems. several techniques have been devised at cell level to make cryptographic vlsi systems resistant against these attacks. therefore,devising a technique to attain both low energy consumption and low area seems to be very appealing and necessary. this work,proposes a new dual-rail pre charge logic style whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow without any constraints on the routing of complementary wires. the main drawback in the existing secure logic styles were additional area this will be reduced in ddpl by using two control signals. these ideas are implemented using t spice tool,a significant improvement in energy consumption up to 50 times and an area reduction up to 60% attacks are observed when compared to the existing logic styles.