voltage difference technique in junctionless tunneling fet for suppression of ambipolar conduction controlling

A detailed study of a novel configuration for junctionless tunneling fet (j-tfet) with extremely low off- (ioff) and ambipolar current (iamb) is reported in this paper. in order to achieve desirable on/off current ratio (ion/ioff), we have employed voltage difference technique on the gate electrode based on the potential distribution benefits. main and side gates with an optimum voltage difference creates a stepped potential profile along the channel. this raises the drain side’s bands, reduces the electric field, puts restriction on the flow of charge carriers, and finally remarkable reduction of iamb from 6.52×10-10 a/µm to 1.14×10-17 a/µm. also an extremely low subthreshold swing (ss) (22 mv/dec) is achieved thanks to the sharp transition from off- to the on-state. finally we have investigated the electrical performance of the proposed device for sub-30 nm channel length to examine its immunity against short channel effects. therefore, our approach renders the novel structure more desirable for the future low power applications.