Design of a new BPSK modulator

In recently, the design of modulator algorithms for wireless communication systems by using digital circuits is widely realized. moreover, it is crucial that resource utilization of the selected algorithm is reduced. in this paper, a modulator architecture which has lower ram bit that of conventional bpsk is proposed for bpsk (binary phase shift keying) modulation technique that is used widely in wireless communication systems. the architecture can achieve to save ram bit utilization by up to 87.5% with respect to conventional bpsk. in addition, a real-time message signal is applied on adc (analog to digital converter) which is integrated on altera de-0 nano fpga (field programmable gate array) in the paper. it is shown that proposed structure is practically realizable by achieving of message signal in output of dac (digital to analog converter) after modulation and demodulation processes.