enhancing high-performance computing: a comprehensive study on dual-doped source/drain reconfigurable field effect transistor

Background and objectives: in this study, a reconfigurable field-effect transistor has been developed utilizing a multi-doped source-drain region, enabling operation in both n-mode and p-mode through a simple adjustment of electrode bias. in contrast to traditional reconfigurable transistors that rely on schottky barrier source/drain with identical schottky barrier height, the suggested device utilizes a straightforward fabrication process that involves physically multi-doped source and drain. the proposed structure incorporates a bilayer of n+ and p+ in the source and drain regions.methods: the device simulator silvaco (atlas) is utilized to conduct the numerical simulations.results: the transistor exhibits consistent transfer characteristics in both modes of operation. the influence of key design parameters on device performance has been analyzed. a notable aspect of this transistor is the integration of an xnor logic gate within a single device, rendering it suitable for high-performance computing circuits. the findings indicate that on-state currents of 142 µa/µm and 57.2 µa/µm, along with on/off current ratio of 8.68×107 and 3.5×107, have been attained for n-mode and p-mode operation, respectively.conclusion: a single-transistor xnor gate design offers potential advantages for future computing circuits due to its simplicity and reduced component count, which could lead to smaller, more energy-efficient, and potentially faster computing systems. this innovation may pave the way for advancements in low-power and high-density electronic devices.