fast and efficient hardware implementation of 2d gabor filter for a biologically-inspired visual processing algorithm

Background and objectives: programmable logic devices, such as field programmable gate arrays, are well-suited for implementing biologicallyinspired visual processing algorithms and among those algorithms is hmax model. this model mimics the feedforward path of object recognition in the visual cortex. methods: hmax includes several layers and its most computation intensive stage could be the s1 layer which applies 64 2d gabor filters with various scales and orientations on the input image. a gabor filter is the product of a gaussian window and a sinusoid function. using the separability property in the gabor filter in the 0° and 90° directions and assuming the isotropic filter in the 45° and 135° directions, a 2d gabor filter converts to two more efficient 1d filters. results: the current paper presents a novel hardware architecture for the s1 layer of the hmax model, in which a 1d gabor filter is utilized twice to create a 2d filter. using the even or odd symmetry properties in the gabor filter coefficients reduce the required number of multipliers by about 50%. the normalization value in every input image location is also calculated simultaneously. the implementation of this architecture on the xilinx virtex6 family shows a 2.83ms delay for a 128×128 pixel input image that is a 1.86x-speedup relative to the last best implementation. conclusion: in this study, a hardware architecture is proposed to realize the s1 layer of the hmax model. using the property of separability and symmetry in filter coefficients saves significant resources, especially in dsp48 blocks.