a 12 bit 76ms/s sar adc with a capacitor merged technique in 0.18µm cmos technology

A new highresolution and highspeed fully differential successive approximation register (sar) analog to digital converter (adc) based on capacitor merged technique is presented in this paper. the main purposes of the proposed idea are to achieve highresolution and highspeed sar adc simultaneously as well. it is noteworthy that, exerting the suggested method the total capacitance and the ratio of the msb and lsb capacitor are decreased, as a result, the speed and accuracy of the adc are increased reliably. therefore, applying the proposed idea, it is reliable that to attain a 12bit resolution adc at 76ms/s sampling rate. furthermore, the power consumption of the proposed adc is 694µw with the power supply of 1.8 volts correspondingly. the proposed postlayout sar adc structure is simulated in all process corner condition and different temperatures of 50℃ to +50℃, and performed using the hspice bsim3 model of a 0.18µm cmos technology.