a 2-bit full comparator design with minimum quantum cost function in quantum-dot cellular automata

In recent years, reduction of the complementary metal-oxide-semiconductor (cmos) circuit's feature size has posed significant challenges, such as current loss and leakage and high power consumption. consequently, further size reduction of cmos technology is not feasible. as an emerging nanoscale technology, quantum-dot cellular automata (qca) can be utilized in the near future for designing computers and very-large-scale integration (vlsi) circuits. qca technology makes it possible to design low-power, high-performance, and area-efficient logical circuits. a comparator function is a digital logical function which compares and evaluates whether or not a bit is greater than, smaller than or equal to the other bit (half comparator). a full comparator has a third input which shows the result of the previous step. half and full comparators play an essential role in cpu architecture. the current paper proposes a full comparator circuit based on qca and a new quantum cost function. in addition, a 2-bit comparator is presented based on the introduced full comparator. employing the new quantum cost function, the present study compares the proposed full comparator design with previously presented designs in terms of area, delay, and complexity. comparisons show that the proposed design occupy less area and produces less delay and so is more suitable for usage in cpu design.