A Novel Scheme for Fault-Tolerant and Higher Capacity Network on Chip

As cmos technology scales down, noc (network on chip) gradually becomes the mainstream of onchipcommunication. in this paper we present a methodology to design fault-tolerant routing algorithms for regulardirect interconnection networks. it supports fully adaptive routing, does not degrade performance in the absence offaults, and supports a reasonably large number of faults without significantly degrading performance. consequently,this work examines fault tolerant communication algorithms for use in the communication networks including nocdomain. before two different flooding algorithms, a random walk algorithm and an intermediate node algorithmhave been investigated. the first three algorithms have an exceedingly high communication overhead and cause hugecongestion in usual traffics. the fourth one which is intermediate node algorithm is a static fault-tolerant algorithmwhich focuses on the faults knowing in advance where they are located. we have developed a new dynamic algorithmbased on intermediate node concept and stress value concept to overcome all of blind sides of mentioned algorithms.we have designed a switch/router base on this algorithm and simulated by max plus ii tool and verified it on amesh noc in xilinx environment.