Reduction the Number of Power Electronic Devices of a Cascaded Multilevel Inverter Based on New General Topology

In this paper, a new cascaded multilevel inverter by capability of increasing the number of output voltage levels with reduced number of power switches is proposed. the proposed topology consists of series connection of a number of proposed basic multilevel units. in order to generate all voltage levels at the output, five different algorithms are proposed to determine the magnitude of dc voltage sources. reduction of the used power switches and the variety of dc voltage sources magnitudes are two main advantages of the proposed topology. these results are obtained by comparison of the proposed inverter with the h-bridge cascaded multilevel inverter and one of recently presented topologies. the remarkable ability of the proposed topology with its algorithms in generating all voltage levels (even and odd) is verified through pscad/emtdc simulation and experimental results of a 17-level inverter.