A Hardwired Discrete Simulation Algorithm

The architecture of a hardwired simulator for implementation of a discrete event-driven simulation of digital systems at the logic level is presented. in the design of this system, attempts have been made to utilize techniques of high performance computing to have a system capable of simulating the digital circuits rapidly. the centralized event-driven simulation algorithm chosen here, has the advantages of being efficient and conceptually straightforward. the high reliability of the simulator has been taken care of through a collection of handshake signals between each two of the three main modules.