A Programmable GPS Receiver with Test Circuits in 0.18 /xm CMOS

A 0.18 /im single chip gps receiver, with 19.5 ma current consumption, is implemented in 6.5 mm2. low-if architecture was used for a high level of integration and low power consumption. a serial input digital control, with additional testing structure, not adding more than 4% to the si area, is used in the actual rf circuits, in case of problems, minimizing the number of si runs.