Read stability and power analysis of a proposed novel 8 transistor static random access memory cell in 45 nm technology

This paper presents analysis of the static noise margin (snm), power dissipation, access time and dynamic noise margin of a novel low power proposed 8t static random access memory (sram) cell for read operations. in the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. simulation results for the read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other sram cells, reported in different literatures. it is shown that the proposed sram cell has better static noise margin and dissipates less power in comparison to other sram cells. analog and schematic simulations have been done in a 45 nm environment with the help of microwind 3.1, using the bsimm4 model.