High speed multiplier using high accuracy floating point logarithmic number system

Asic implementation of a high speed multiplier using a high accuracy floating point logarithmic number system is reported in this paper. the most popularly used techniques for computing logarithmic calculations for digital signal processors are: lookup table based implementation, polynomial approximation, and taylor series expansion. but, all these techniques suffer from low accuracy, due to the choice of having only lower order terms of the expanded series. in the present work, logarithmic conversion is implemented by a floating point (ieee-754 single precision) converting methodology, thereby eliminating series expansion, which eventually results in high accuracy. the improvement in speed, by avoidance of carry propagation, was achieved through canonical signed digit code (csdc) implementation, while the high accuracy was achieved through an error minimization circuitry especially designed for this purpose. the functionality of these circuits was checked, and performance parameters, like propagation delay and dynamic power consumption, were calculated by spice spectre using 90 nm cmos technology. the propagation delay and power consumption of the resulting (128 × 128) bit multiplier (divider) was only ~ 93 ns and ~ 80 mw, respectively, for a layout area of ~ 25 mm^2. this implementation offered a significant improvement in terms of accuracy, delay and power from those reported earlier.