Minimum power Miller-compensated CMOS operational amplifiers

A new approach for the design of two-stage miller-compensated cmos op amps is presented. the paper studies the basic relations between power consumption, unitygain bandwidth, the biasing region, technology parameters, and the external capacitive load. as a result, simple and efficient design guides are provided to achieve the minimum possible power consumption for the given specifications and for short-channel devices. it is shown that the conventional design procedures do not always result in minimum power op amps. the presented results are also verified by spectre simulations.