a low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme

The sampling rate plays a key role in wireless applications at very high-frequency range. flash analog-to-digital converter (adc) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. a state-of-the-art divide and collate (dnc) algorithm is proposed to design the flash adc at subranging levels. the offset voltage is kept at a minimum through the comparators used for coarse and fine conversion separately. the kick-back noise is also reduced by using sample and hold switches at the input. the 10-bit adc architecture is designed with 45 -nm cmos technology and analyzed in the spectre environment. a trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mv/’c. the design improves the inl by 0.42 lsb and dnl by 0.3 lsb. signal-to-noise-and-distortion (sndr) ratio and spurious-free dynamic range (sfdr) are 51.8 db and 62 db respectively at a frequency range near the nyquist rate with a supply voltage of 1 v and input frequency of 500 mhz. subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.