Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

Resistive random access memory (rram) is gaining attention as one of the prominent contenders to replace the conventional memory technologies such as sram, dram and flash. this emerging memory uses scaled cmos devices (22 nm or less) to form the peripheral circuits such as decoder and sense amplifier; while a non-cmos device known as memristor is used to form the cell array. although potentially becoming the main future memory, rram is anticipated to be impacted by the high manufacturing defect density that in turn might lead to quality and reliability problems. this paper presents the initial work towards producing a high quality and reliable rram devices. a design and simulation of three memristor spice models published in prominent literatures were performed using silvaco eda simulation tool. the aim is to identify the optimal model to be used in our rram design, which is based on 22 nm cmos technology. performance analysis shows that the model proposed by d. biolek is suitable to be used in our rram design.