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   Optimization AES S-box/Inv S-box using FPGA implementation  
   
نویسنده hamzah h. ,ahmad n. ,hairol jabbar m. ,soon c.f.
منبع journal of telecommunication, electronic and computer engineering - 2017 - دوره : 9 - شماره : 3-8 - صفحه:133 -136
چکیده    Advanced encryption standard (aes) is a common symmetric encryption algorithm and widely implemented in wireless local area network (wlan),radio frequency identification (rfid) tags and bluetooth controller as the default choice for security services in its application. substitution box (s-box) is a non-linear transformation and the core of aes implementation which consumed most of the power in aes hardware. this paper presents a low-complexity design methodology for the s-box/ inverse s-box (inv s-box) implemented in field-programmable gate array (fpga) using composite field arithmetic and quartus ii as a tool to obtain simulation results through verilog hardware description language (hdl). this design utilized 94 slices with the hardware cost of the s-box/invs-box is about 172 logic gates,with the power consumption of 31mw and the throughput is 1.6gbps obtained through calculation. the design is suitable for the portable device application which requires data security with a low area and power consumption.
کلیدواژه AES; Composite field; FPGA; S-box/InvS-box
آدرس department of electronic engineering,faculty of electrical and electronic engineering,universiti tun hussein onn malaysia,parit raja,batu pahat,johor, Malaysia, department of electronic engineering,faculty of electrical and electronic engineering,universiti tun hussein onn malaysia,parit raja,batu pahat,johor, Malaysia, department of computer engineering,faculty of electrical and electronic engineering,universiti tun hussein onn malaysia,parit raja,batu pahat,johor, Malaysia, department of electronic engineering,faculty of electrical and electronic engineering,universiti tun hussein onn malaysia,parit raja,batu pahat,johor, Malaysia
 
     
   
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