Development design of fault-tolerant soft-core based on error correction code in FPGA

This paper presented the development of fault-tolerant soft-core that was implemented based on error correction code (ecc). a simulation of behavioral module was carried out using xilinx ise design suite software. the design focuses on fault-tolerant hamming code,single-error-correction double-error-detection (sec-ded) code and triple modular redundancy (tmr) code that is synthesizable in the field of programmable gate array (fpga) verilog. the faults have been injected into the fault-tolerant module. the experiment results were compared as the error detection and the error recovered simulated as simulation results.