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A novel parallel hardware architecture for inter motion estimation in HEVC
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نویسنده
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dinh c. ,nguyen t. ,pham c. ,nguyen p. ,duong d. ,phung h. ,pham t. ,nguyen t.
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منبع
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journal of telecommunication, electronic and computer engineering - 2017 - دوره : 9 - شماره : 1-3 - صفحه:83 -88
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چکیده
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High efficiency video coding (hevc) standard,generated by itu,can provide compression ratio twice more than current h.264/mpeg-4. to date,only a few hardware have been implementated for integer motion estimation (ime) to date. in this paper,a parallel hardware architecture for ime in hevc encoder is proposed. this design uses rot-w-diamond (rwd) algorithm to reduce computational load and parallelism to improve processing speed. therefore,this design can reach 4k (4096×2160) video in real time at 60 frames per second (fps) and achieve the frequency of 125mhz.
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کلیدواژه
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FPGA; H.264/MPEG-4; H.265/HEVC; Inter motion estimation (IME); Motion estimation (ME)
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آدرس
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school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam, school of electronics and telecommunications,hanoi university of science and technology,hanoi, Viet Nam
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Authors
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