an area-efficient broadband balun-lna-mixer front-end for multi-standard receivers

An areaefficient wideband receiver frontend for multistandard receivers is presented. to handle large input signal levels, dual gain modes are employed in the lna stage. for input signals lower than 17.5 dbm, a noisecanceling balun cgcs lna is employed. the lna features a local feedback loop to reduce power consumption. for input signals in the range of from 17.5 to 5.2 dbm, the cgcs lna is bypassed with a balun unitgain inverter stage. the proposed frontend shows better than 12 db input matching for both gain modes in the frequency range of 0.43.4 ghz. due to the lack of offchip balun, the proposed frontend consumes low area. moreover, the full differential structure leads to enhanced linearity performance. the postlayout simulation results in rf cmos 0.18 µm process shows the conversion gain of 24.5/13.06 db in hg/lg modes. the minimum dsb nf is 3.77/9.84 db, and the third input intercept point (iip3) is 7.29/1.8 dbm. the circuit dissipates 12.93 mw with an active area of 0.073 mm^2.

An area-efficient broadband balun-LNA-mixer front-end for multi-standard receivers

An areaefficient wideband receiver frontend for multistandard receivers is presented. To handle large input signal levels, dual gain modes are employed in the LNA stage. For input signals lower than 17.5 dBm, a noisecanceling balun CGCS LNA is employed. The LNA features a local feedback loop to reduce power consumption. For input signals in the range of from 17.5 to 5.2 dBm, the CGCS LNA is bypassed with a balun unitgain inverter stage. The proposed frontend shows better than 12 dB input matching for both gain modes in the frequency range of 0.43.4 GHz. Due to the lack of offchip balun, the proposed frontend consumes low area. Moreover, the full differential structure leads to enhanced linearity performance. The postlayout simulation results in RF CMOS 0.18 µm process shows the conversion gain of 24.5/13.06 dB in HG/LG modes. The minimum DSB NF is 3.77/9.84 dB, and the third input intercept point (IIP3) is 7.29/1.8 dBm. The circuit dissipates 12.93 mW with an active area of 0.073 mm2.