A Novel Design of Reversible Multiplier Circuit

Adders and multipliers are two main parts of arithmetic units of computer hardware and play important role in reversible computations. this paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced “partial product generation circuits” (ppgc) with peres gates only without duplicating gates. again, an optimized peres full adder reversible gate is used in “reversible parallel adder” (rpa) part with accompaniment with the carry save adder technique. comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves the quantum parameters. the proposed design shows lower quantum cost and depth with the help of a novel design in ppgc. the circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. moreover, the number of gates, garbage input and output has no change regarding to the best compared design. the proposed multiplier can be generalized as an n×n bit multiplication.