design and performance analysis of junctionless vertically stacked gate all around transistor

This work presents a comprehensive analysis and scaling characteristics of junctionless (jl) gate-all-around (gaa) device using vertically stacked nanosheet architecture  (jlvs gaans). the gate length (lg) ranging from 30 nm down to 3 nm were investigated using two gate dielectric materials such as silicon dioxide (sio₂) and hafnium dioxide (hfo₂). the electrical performance of this device is evaluated using direct current (dc) measurements including sub-threshold swing (ss), drain-induced barrier lowering (dibl), on current (ion), off current (ioff), and the ion/ioff ratio. the results show that the proposed device with ultra-scaled dimensions of 5 nm and 3 nm demonstrated excellent electrical properties, with ioff reaching 10^-8 a at 5 nm and 10^-11 a at 3 nm, while ion remained at 10^-6 a for both dimensions when hfo2 used as the gate dielectric material. these findings emphasize the crucial role of high-k materials in enhancing device performance at reduced gate length and explore the scaling flexibility of the proposed structure by investigating parameters such as transconductance (gm) and transconductance generation factor (tgf). the results demonstrate that hfo2 is superior to sio2 in reducing leakage current and maintaining high on-state drain current ion, making it highly effective for advanced nanoelectronic devices.