investigation and analysis of dual metal gate overlap on drain side tunneling field effect transistor with spacer in 10nm node

This paper investigates the electrical behavior and performance of a dual metal gate overlap on drain side tunnel field effect transistor with spacer (dmg-ods-tfet) in 10 nanometer technology. in this design, the utilization of two different metals to create the gate effectively maintains electrostatics and minimizes gate leakage current. this structure is formed by silicon dioxide and hafnium oxide as dielectric materials. the drain current characteristics such as subthreshold swing, on-state current, off-state leakage current, and transconductance are calculated for the proposed device using the available two-dimensional numerical device simulator silvaco tool. the characteristics of the proposed device vary with changes in channel length, doping concentrations of the drain and source, and the thickness of the oxide layer. this structure shows a lower off current, and better on-to-off current ratio with improved drain current. consequently, the proposed design effectively balances gate control and leakage current, resulting in superior to conventional and dual metal gate devices. based on improved performance parameters, this proposed structure is suitable for high-frequency applications.