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Low-Power Adder Design for Nano-Scale CMOS (Short Paper)
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نویسنده
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Talebiyan S. R. ,Hosseini-Khayat S.
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منبع
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iranian journal of electrical and electronic engineering - 2009 - دوره : 5 - شماره : 3 - صفحه:180 -184
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چکیده
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A fast low-power l-bit full adder circuit suitable for nano-scale cmosimplementation is presented. out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. the design has been simulated and evaluated using the 65nm ptm models.
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کلیدواژه
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Nano-Scale CMOS Technology ,Static Power Consumption ,AdderSubcomponents
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آدرس
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ferdowsi university of mashhad, Department of Electrical Department, ایران, ferdowsi university of mashhad, Department of Electrical Department, ایران
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پست الکترونیکی
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shk@alum.wustl.edu
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Authors
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