proposing very low power three-valued flip-flops by using cntfet transistors

The scaling limitations of complementary metal-oxide-semiconductor (cmos) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. one of these structures is multi-valued circuits. in this paper, we will first study carbon nanotube transistors (cnt). cnt transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. leveraging the insights gained from our analysis, we propose a novel d-type flip-flop structure. the presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations.  overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. however, they showcase a 96.1% reduction in power-delay product (pdp) compared to the other structures. the number of transistors is also 8.3% less than other structures. additionally, their figure of merits (fom) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance.