ultra-low power 5t-sram cell design using different cntfet for exploiting read/write assist techniques

In today’s technological environment, designing the static random access memory (sram) is most vital and critical memory devices. in this manuscript, two kinds of 5tsram are designed using different cntfet such as dual-chiralitygate all around (gaa) cntfet and ballistic wrap gate cntfet based 5t sram cell designs for enhancing the read/write assist process. here, the proposed dual-chiralitygaa-cntfet based 5t-sram has two cross-coupled inverters using one access transistor that is connected to the bit line (bl) and word line (wl) through minimum supply voltage. instead of cross-coupled inverter circuit, the bwg-cntfet based 5t-sram cell is intended for achieving less power and improved read/write assist process. also, one transistor is executed as low-threshold (lvt) device in the proposed bwg-cntfet based 5t-sram. thus, proposed two kinds of 5t sram cells increases the read/write assist operation and reduce the leakage current/ power. the simulation of the proposed two kinds of 5t sram cell is done by hspice simulation tool and the performance metrics are calculated. therefore, the proposed dual-chiralitygaa-cntfet based 5t-sram cell design has attained 11.31%, 51.47% lower read delay, 44.44%, 26.33% lower write delay, 36.12%, 45.28% lower read power, 34.5% , 22.41% lower write power, 37.4%, 15.3% higher read snm and 35.8%, 12.09% higher write snm than double gate carbon nanotube field effect transistors (dg cntfet) and state-of-art method respectively. similarly, the proposed bwg-cntfet 5t sram cell design has attained 45.53%, 38.77% lower write delay, 56.67%, 45.64% lower read delay, 58.4%, 56.75% lower read power, 49.66%, 28.56% lower write power, 35.32%, 12.7% higher read snm and 45.8%, 15.6% higher write snm than reduced power with enhanced speed (rpes) approach and state-of-art method respectively.