design and implementation of high speed and low power 12-bit sar adc using 22nm finfet

Successive approximation register (sar) analog to digital converter (adc) architecture comprises submodules such as comparator, digital to analog converters (dac), and sar logic. each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. design strategies for optimum design of circuits considering 22nm finfet technology meeting area, timing, power requirements, and adc metrics are presented in this work. operational transconductance amplifier (ota) based comparator, 12-bit two-stage segmented resistive string dac architecture, and low power sar logic are designed and integrated to form the adc architecture with a maximum sampling rate of 1 gs/s. circuit schematic is captured in cadence environment with optimum geometrical parameters and performance metrics of the proposed adc are evaluated in matlab environment. differential nonlinearity and integral nonlinearity metrics for the 12-bit adc are limited to +1.15/-1 lsb and +1.22/-0.69 lsb respectively. enob of 10.1663 with snr of 62.9613 db is achieved for the designed adc measured for conversion of input signal of 100 mhz with 20db noise. adc with sampling frequency up to 1 gsps is designed in this work with low power dissipation of less than 10 mw.