A Novel and Efficient Hardware Implementation of Scalar Point Multiplier

A new and highly efficient architecture for elliptic curve scalar point multiplication which is optimized for the binary field recommended by nist is presented. to achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the lopez-dahab scalar point multiplier carefully such that sequentially executed operations are separated into parallel operations and operations in the critical path are diverted to noncritical paths. with g=41, the proposed design is capable of performing a field multiplication over the extension field with degree 163 in 11.92 ìs with the maximum achievable frequency of 251 mhz on xilinx virtex-4 (xc4vlx200) while 22% of the chip area is occupied, where g is the digit size of the underlying digit-serial finite field multiplier.