switched-capacitor dynamic threshold pmos (sc-dtpmos) transistor for high speed sub-threshold applications

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. a new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. the proposed switched-capacitor dynamic threshold pmos (sc-dtpmos) scheme employs a capacitor along with an nmos switch in order to effectively reduce the threshold voltage of a pmos transistor. the proposed structure improves the propagation delay of a circuit and is much suitable for those circuits with high switching factor. post layout simulation results using tsmc 180 nm cmos technology at 0.2v supply voltage shows 45% improvement in delay as well as 25% less power consumption at the cost of only 53% more occupied area.